Gate array circuit for decoding circuits

ABSTRACT

A decoder circuit for decoding different combinations of supplied original input address bits, comprising at least one predecode circuit responsive to the original input address bits for producing predecoded signal bits from the input address bits, and a plurality of decoder units including at least one decoder unit responsive to at least two different combinations of the original input address bits, wherein the decoder units comprises a decoder unit responsive to selected ones of the predecoded signal bits alone and a decoder unit responsive to at least one of the predecoded signal bits and at least one of the original input address bits.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices and, moreparticularly, to a decoder circuit for use in a semiconductor memorydevice such as a read-only memory (ROM) or a random-access memory (RAM)which per se is well known in the art.

BACKGROUND OF THE INVENTION

A certain type of address decoder circuit for use in a semiconductormemory device such as a ROM or RAM device consists of decoder units of anumber less than the number of the possible combinations of the bitsforming an address signal to be supplied to the decoder circuit. Atypical example of such a decoder circuit is the one used for a ROMdevice which is incorporated in a microprocessor to storemicroprogramming codes therein. Such a decoder circuit is directlyresponsive to the original input address signals so that, where each ofthe original input address signal consists of six bits, a maximum of 2⁶=64 different combinations or sequences of bits could be used in thedecoder circuit. In comparison with such a large number of possibledecoder outputs, the decoder circuit actually has a far smaller numberof outputs such as, for example, only twelve outputs and, for thisreason, requires the provision of a disproportionately large number ofactive devices or transistors. Such a large number of active devicesused in the decoder circuit inevitably results in correspondingly largeamounts of capacitances provided by the diffusion regions of theindividual active devices and accordingly in reduction in the switchingspeed achievable of the decoder circuit.

An address decoder circuit of the described type thus sometimes uses apredecode scheme for the purpose of reducing the number of thetransistors to be used in the decoder circuit and thereby increasing theswitching speed achievable of the circuit. The decoder circuit toimplement such a scheme comprises a suitable number of 2-bit predecodecircuits which are directly responsive to the original input signalbits. Each of these 2-bit predecode circuits is operative to predecodeneighboring two of the original input address bits by producing a totalof four different logic ANDs of the two bits and the inverted versionsof the two bits. The predecoded signal bits thus produced by the 2-bitpredecode circuits are used in some of the decoder units so that onlyone of the two original input address bits which have resulted in eachof the predecoded signal bits is effective in the particular decoderunit with the other of the two bits virtually neglected from use. Theresult is accordingly that there exits address bits which are not usedin the decoder circuit. Such a scheme of the decoder circuit inevitablyresults in irregularities in the geometrical topology of the decodercircuit fabricated on a semiconductor chip.

It is, thus, an important object of the present invention to provide animproved decoder circuit which is composed of a minimized number ofactive devices to achieve an increased switching speed of the decodercircuit.

It is another important object of the present invention to provide animproved predecode decoder circuit which effectively uses the originalinput address bits supplied to the decoder circuit.

SUMMARY OF THE INVENTION

In accordance with one outstanding aspect of the present invention,there is provided a decoder circuit for decoding different combinationsof supplied original input signal bits, comprising (a) at least onepredecode circuit responsive to the original input signal bits forproducing predecoded signal bits from the input signal bits, and (b) aplurality of decoder units including at least one decoder unitresponsive to at least two different combinations of the original inputsignal bits, characterized in that the decoder units comprises a decoderunit responsive to the combination of at least one of the predecodedsignal bits and at least one of the original input signal bits.

In accordance with another outstanding aspect of the present invention,there is provided a decoder circuit for decoding different combinationsof supplied original input signal bits, comprising (a) at least onepredecode circuit responsive to the original input signal bits forproducing predecoded signal bits from the input signal bits, and (b) aplurality of decoder units including at least one decoder unitresponsive to at least two different combinations of the original inputsignal bits, wherein the decoder units comprises a decoder unitresponsive to selected ones of the predecoded signal bits alone and adecoder unit responsive to at least one of the predecoded signal bitsand at least one of the original input signal bits.

In accordance with still another outstanding aspect of the presentinvention, there is provided a semiconductor decoder circuit including aplurality of decoder units for decoding different combinations ofsupplied original input signal bits, comprising (a) a first set ofsignal lines formed on a semiconductor structure, the first set ofsignal lines comprising a first group of signal lines connected to asource of a first predetermined voltage and a second group of signallines connected to a source of a second predetermined voltage, (b) asecond set of signal lines formed on a semiconductor structure andextending substantially at right angles to the first set of signallines, the second set of signal lines comprising a third group of signallines respectively responsive to predecoded signal bits predecoded fromselected ones of the original input signal bits and a fourth group ofsignal lines respectively responsive to selected ones of the originalinput signal bits, (c) a first set of field-effect transistorsselectively connected in series to the source of the first predeterminedvoltage along each of the signal lines of the first group, each of thefirst set of field-effect transistors being of one channel conductivitytype, and (d) a second set of field-effect transistors selectivelyconnected in parallel to the source of the second predetermined voltagealong each of the signal lines of the second group, each of the secondset of field-effect transistors being of the channel conductivity typeopposite to the one channel conductivity type, each of the second set offield-effect transistors having their gates selectively connected to thesignal lines of the third and fourth groups, (e) the first set offield-effect transistors arranged along each of the signal lines of thefirst group and the second set of field-effect transistors arrangedalong each of the signal lines of the second group implementing each ofthe decoder units.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawbacks of a prior-art address decoder circuit and the featuresand advantages of a decoder circuit according to the present inventionwill be more clearly understood from the following description taken inconjunction with the accompanying drawings in which:

FIG. 1 is a circuit diagram showing a typical known example of anaddress decoder circuit used for a ROM device storing microprogrammingcodes in a microprocessor;

FIGS. 2A and 2B are address maps depicting the schedules in accordancewith which the decoder units of the decoder circuit shown in FIG. 1 areto produce output signal bits in response to the original address bitsinput to the decoder circuit, FIG. 2A showing such schedules innon-matrix form and FIG. 2B showing similar schedules in matrix form;

FIG. 3 is a circuit diagram showing a preferred example of an addressdecoder circuit which implements a two-bit predecode scheme;

FIG. 4 is a schematic diagram showing the logical configuration of apreferred embodiment of a decoder circuit according to the presentinvention; and

FIG. 5 is a circuit diagram showing a preferred example of the circuitarrangement implementing the logical configuration of the embodimentillustrated in FIG. 4.

DESCRIPTION OF THE PRIOR ART

As has been noted at the outset of the description, a certain type ofaddress decoder circuit for use in a semiconductor memory deviceconsists of decoder units of a number less than the number of thepossible combinations of the bits forming an address signal to besupplied to the decoder circuit. FIG. 1 of the drawings shows a typicalexample of such a decoder circuit. The decoder circuit herein shown isused for a ROM device incorporated in a microprocessor for storingmicroprogramming codes therein and is by way of example assumed to bedesigned for use with a 12-word ROM device (not shown). The decodercircuit is made up of a number of n-channel field-effect transistorsrespectively denoted by N₀₁ to N₂₇ and p-channel field-effecttransistors respectively denoted by P₀₁ to P₂₇. These n-channel andp-channel N₀₁ to N₂₇ and P₀₁ to P₂₇ are arranged to form twelve decoderunits D₀, D₁, D₂, ... D₁₁ each including a plurality of full CMOS(complementary metal-oxide-semiconductor) inverters implemented by thefield-effect transistors N₀₁ to N₂₇ and P₀₁ to P₂₇. The decoder unitsD₀, D₁, D₂, ... D₁₁ further include logic inverters I₀ to I₁₁,respectively, which provide output address bits of the individualdecoder units D₀ to D₁₁, respectively. The decoder units D₀ to D₁₁ areresponsive directly to original, viz., supplied address signals througha total of twelve signal input lines which consist of six linesrespectively responsive to supplied address bits A₀ to A₅ and six linesrespectively responsive to the inverted versions A₀ to A₅ of thesupplied address bits A₀ to A.sub. 5. Each of the decoder units D₀ toD₁₁ consists of n-channel MOS field-effect transistors connected inseries between ground and each of the logic inverters I₀ to I₁₁ andp-channel MOS field-effect transistors connected in parallel between asource of a supply voltage V_(CC) and each of the inverters I₀ to I₁₁ asshown. The logic inverters I₀ to I₁₁ of the decoder units D₀ to D₁₁ arerespectively connected to the word lines of the memory cell array (notshown).

The n-channel field-effect transistors N₀₁ to N₂₇ and p-channelfield-effect transistors P₀₁ to P₂₇ forming the decoder circuit arearranged so that the individual decoder units D₀ to D₁₁ of the decodercircuit are operative to produce output address bits O₁ to O₁₁ inresponse to the supplied address bits A₀ to A₅ and A₀ to A₅ inaccordance with the schedules represented by an address map depicted innon-matrix form in FIG. 2A and in matrix form in FIG. 2B. The sign "X"in the non-matrix address map shown in FIG. 2A indicates anindeterminate or variable bit which may be of either logic "0" or "1"value. In the matrix address map shown in FIG. 2B, the axis of abscissarepresents binary digits 000, 001, 011, . . . 111 (increasing from leftto right) coded by the lower three of the six supplied address bits A₀,A₁, A₂, ... A₅ while the axis of ordinate represents binary digits (000,001, 011, . . . 111 (increasing downwardly) coded by the upper three ofthe address bits A₀ to A₅. As will be seen from these address maps, eachof the decoder units D₂ and D₇ of the address decoder circuit isoperable for selecting one of two different sequences of address bits000010 and 000011 (D₂) or 100100 and 100101 (D₇). On the other hand,each of the decoder units D₃ and D₆ is operable for selecting any one offour different sequences of address bits 000000, 000001, 000010 and000011 (D₃) or 100000, 100001, 100011 (D₆). Furthermore, each of thedecoder units D₄, D₅, D₁₁ and D₁₂ is operable for selecting any one of atotal of eight different sequences of address bits.

When an original input signal A₀ A₁ A₂ A₃ A₄ A₅ in the form of, forexample, 00001X is supplied to the decoder circuit shown in FIG. 1, allthe n-channel field-effect transistors N₁₃, N₁₄, N₁₅, N₁₆ and N₁₇forming part of the decoder unit D₂ are turned on and all the associatedp-channel field-effect transistors P₁₃, P₁₄, P₁₅, P₁₆ and P₁₇ of thedecoder unit D₂ remain in non-conduction states. Under this condition,the decoder unit D₂ produces a logic "1" bit at the output terminal ofthe inverter I₂ as the output signal bit O₂ of the decoder unit D₂.

The known address decoder circuit thus constructed is directlyresponsive to the original input address signals, each of which consistsof six bits yielding a maximum of 2⁶ =64 different combinations orsequences of bits. In comparison with such a large number of possibledecoder outputs, the decoder circuit actually has only twelve outputsand, as a corollary of this, necessitates a disproportionately largenumber of active devices or transistors. As a matter of fact, thedecoder unit D₀ which uses all the supplied address bits A₀, A₁, A₂, . .. A₅ available is composed of a total of twelve transistors whichconsist of the three series connected n-channel field-effect transistorsN₀₁ to N₀₆ and the three parallel connected p-channel field-effecttransistors N₀₁ to N₀₆ and P₀₁ to P₀₆. Even each of the decoder unitsD₁₀ and D₁₁ (as well the decoder units D₅ and D₆, not shown) which usesthe minimum number of input address bits is composed of a total of sixfield-effect transistors N₂₂ to N₂₄ and P₂₂ to P₂₄ or N₂₅ to N₂₇ and P₂₅to P₂₇. Such a large number of field-effect transistors used in thedecoder circuit inevitably results in correspondingly large amounts ofcapacitances provided by the source and drain diffusion regions of thetransistors and accordingly in reduction in the switching speedachievable of the decoder circuit. This drawback of a known addressdecoder circuit is pronounced in a static decoder circuit implemented byfull CMOS configuration as in the case of the prior-art decoder circuitshown in FIG. 1. Whichever of NAND-based logics or NOR-based logics maybe adopted in such a full CMOS address decoder circuit, either then-channel field-effect transistors or the p-channel field-effecttransistors implementing the decoder circuit must be connected inseries. The larger the number of the series connected field-effecttransistors, the lower the performance efficiencies of the individualtransistors and accordingly the lower the switching speed of the entiredecoder circuit.

Thus, an address decoder circuit of the type shown in FIG. 1 sometimesuses a predecode scheme for the purpose of reducing the number of thetransistors to be used in the decoder circuit and thereby increasing theswitching speed achievable of the circuit. FIG. 3 of the drawings showsa preferred example of an address decoder circuit which implements sucha predecode scheme.

The decoder circuit herein shown is arranged to produce output addressbits O₀ to 0₁₁ responsive to original input address bits A₀, A₁, A₂, . .. A₅ also in accordance with the schedules represented by the addressmap of FIGS. 2A or 2B. The decoder circuit is also assumed to comprise atotal of twelve decoder units including the shown decoder units D₂, D₁₀and D₁₁ which are formed by n-channel field-effect transistors N₂₈ toN₃₆ and p-channel field-effect transistors P₂₈ to P₃₆ and which includelogic inverters including the inverters I₂, I₁₀ and I₁₁, respectively.The decoder circuit further comprises first, second and third 2-bitpredecode circuits PD₁, PD₂ and PD₃ which are directly responsive to theoriginal input signal bits A₀, A₁, A₂, ... A₅. Each of these 2-bitpredecode circuits PD₁, PD₂ and PD₃ is operative to predecodeneighboring two bits (A_(2i) and A_(2i+1) where i=0, 1 or 2) of thesupplied original input address bits A₀, A₁, A₂, . . . A₅. The first2-bit predecode circuit PD₁ is responsive to the lower two A₀ and A₁ ofthe original input address bits A₀, A₁, . . . A₅ to produce fourdifferent output bits B₀₀, B₀₁, B₀₂ and B₀₃ respectively representativeof the logic ANDs A₀ ·A₁, A₀ ·A₁ ·A₀ ·A₁ and A₀ ·and 1 of the input bitsA₀ and A₁ and the respective inverted versions thereof. The second 2-bitpredecode circuit PD₂ is responsive to the intermediate two A₂ and A₃ ofthe original input address bits A₀ to A₅ to produce four differentoutput bits B₁₀, B₁₁, B₁₂ and B₁₃ respectively representative of thelogic ANDs A₂ ·A₃, A₂ ·A₃, A₂ ·A₃ of the input bits A₂ and A₃ and therespective inverted versions thereof. The third 2-bit predecode circuitPD₃ is responsive to the intermediate two A₄ and A₅ of the originalinput address bits A₀ to A₅ to produce four different output bits B₂₀,B₂₁, B₂₂ and B₂₃ respectively representative of the logic ANDs A₄ ·A₅,A₄ ·A₅, A₄ ·A₅ and A₄ ·A₅ of the input bits a4 and A₅ and the respectiveinverted versions thereof.

When an original input signal A₀ A₁ A₂ A₃ A₄ A₅ in the form of, forexample, 00001X is supplied to the decoder circuit thus constructed andarranged, the output bits B₀₂, B₀₃, B₁₀ and B₂₀ respectivelyrepresentative of the logic ANDs A₀ ·A₁, A₀ ·A₁, A₂ ·A₃ and A₄ ·A₅ ofthe supplied address bits assume logic "X", "X", "1" and "1" states. Ofthe field-effect transistors forming part of the decoder unit D₂, forexample, of the circuit shown in FIG. 3, the series connected n-channelfield-effect transistors N₃₀ and N₃₁ and one of the parallel connectedn-channel field-effect transistors N₂₈ and N₂₉ are thus turned on andthe series connected p-channel field-effect transistors P₃₀ and P₃₁ andone of the parallel connected p-channel field-effect transistors P₂₈ andP₂₉ are held in non-conduction states. Under this condition, the decoderunit D₂ produces a logic "1" signal at the output terminal of theinverter I₂ as the output signal bit O₂ of the decoder unit D₂ as in theprior-art address decoder circuit shown in FIG. 1.

In the decoder unit D₂ of the circuit shown in FIG. 3, the predecodedsignal bits B₀₂ and B₀₃ produced by the first 2-bit predecode circuitPD₁ are supplied to the parallel combination of the n-channelfield-effect transistors N₂₈ and N₂₉ of the decoder unit D₂ to produce alogic sum or OR, viz., (A₀ ·A₁ +A₀ ·A₁)=A₁ of the supplied bits. Thepredecoded signal bits B₀₂ and B₀₃ are also supplied to the seriescombination of the p-channel field-effect transistors P₂₈ and P₂₉ of thedecoder unit D₂ to produce a logic OR, viz., (A₀ ·A₁)+(A₀ ·A₁)=A₁ of thesupplied bits. Likewise, the predecoded signal bits B₁₀ and B₁₂ producedby the second 2-bit predecode circuit PD₂ are supplied to the parallelconnected n-channel field-effect transistors N₃₂ and N₃₃ and seriesconnected p-channel field-effect transistors P₃₂ and P₃₃ of the decoderunit D₁₀ to produce a logic OR, viz., (A₂ ·A₃ +A₂ ·A₃)=A₂ and a logicOR, viz., (A₂ ·A₃)+(A₂ ·A₃) =A₂ of the supplied bits. In the decoderunit D₁₁, furthermore, a logic OR, viz., (A₂ ·A₃ +A₂ ·A₃) =A₂ isproduced in response to the predecoded signal bits B₁₀ and B₁₂ producedby the second 2-bit predecode circuit PD₂.

In the decoder circuit shown in FIG. 3, the neighboring two A_(2i) andA_(2i) of the supplied original input address bits A₀, A₁, A₂, ... A₅are thus predecoded by each of the of 2-bit predecode circuits PD₁, PD₂and PD₃ into signal bits B₀₀ to B₂₃ each of which is provided by thelogic AND of the supplied address bit A_(2i) or the inverted versionthereof and the supplied address bit A_(2i+1) or the inverted versionthereof. The predecoded signal bits B₀₀ to B₂₃ are used in the decoderunits D₂, D₃, D₄, D₅, D₆, D₇, D₁₀ and D₁₁ so that only one of the twooriginal input address bits such as, for example, the address bit A₁ forthe decoder unit D₂ or the address bit A₂ for the decoder unit D₁₀ orD₁₁ is effective in the particular decoder unit. This means that theother of the two bits A_(2i) and A_(2i) is virtually neglected from use.Such a scheme of the decoder circuit results in irregularities in thegeometrical topology of the decoder circuit fabricated on asemiconductor chip because of the fact that the individual decoder unitsD₀, D₁, D₂, . . . D₁₁ each of which should be configured by activedevices and interconnections patterned with irregularity will differ intopology from one circuit to another.

The present invention contemplates elimination of such a probleminherent in a two-bit predecode decoder circuit of the described nature.Accordingly, the goal of the present invention is to provide an improveddecoder circuit which is composed of a minimized number of activedevices to achieve an increased switching speed of the decoder circuitand which effectively uses the original input address bits supplied tothe decoder circuit, as previously noted.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 4 of the drawings shows the logical configuration of a preferredembodiment of a decoder circuit according to the present invention. Thedecoder circuit herein shown is also assumed to be designed for use witha 12-word ROM device (not shown) by way of example and thus comprisestwelve decoder units D₀, D₁, D₂, . . . D₁₁. The decoder units D₀, D₁,D₂, . . . D₁₁ in turn comprise two-input and three-input logic NANDgates G₀, G₁, G₂, . . . G₁₁, respectively, and logic inverters I₀, I₁,I₂, ... I₁₁ respectively connected to the output terminals of the NANDgates G₀, G₁, G₂, . . . G₁₁ to provide output address bits of theindividual decoder units D₀ to D₁₁.

The decoder circuit embodying the present invention further comprisesfirst, second and third 2-bit predecode circuits PD₁, PD₂ and PD₃ whichare directly responsive to original input signal bits A₀, A₁, A₂, . . .A₅ and the inverted versions A₀, A₁, A₂, . . . A₅, respectively,thereof. Each of these 2-bit predecode circuits PD₁, PD₂ and PD₃ isoperative to predecode neighboring two bits A_(2i) and A_(2i+1) of thesupplied original input address bits A₀, A₁, A₂, . . . A₅ similarly totheir counterparts in the decoder circuit described with reference toFIG. 3. Thus, the first 2-bit predecode circuit PD₁ is responsive to thelower two A₀ and A₁ of the original input address bits A₀, A₁, . . . A₅to produce four different output bits B₀₀, B₀₁, B₀₂ and B₀₃ respectivelyrepresentative of the logic ANDs A₀ ·AHD 1, A₀ ·A₁, A₀ ·A₁ and A₀ ·A₁ ofthe input address bits A₀ and A₁ and the respective inverted versionsthereof. The second 2-bit predecode circuit PD₂ is responsive to theintermediate two A₂ and A₃ of the original input address bits A₀ to A₅to produce four different output bits B₁₀, B₁₁, B₁₂ and B₁₃ respectivelyrepresentative of the logic ANDs A₂ ·A₃, A₂ ·A₃, A₂ ·A₃ and A₂ ·A₃ ofthe input address bits A₂ and a3 and the respective inverted versionsthereof. The third 2-bit predecode circuit PD₃ is responsive to theintermediate two A₄ and A₅ of the original input address bits A₀ to A₅to produce four different output bits B₂₀, B₂₁, B₂₂ and B₂₃ respectivelyrepresentative of the logic ANDs A₄ ·A₅, A₄ ·A₅, A₄ ·A₅ ·A₅ of the inputaddress bits A₄ and A₅ and the respective inverted versions thereof. Thedecoder circuit thus comprising the twelve NAND gates G₀ to G₁₁ areresponsive to the original input address bits A₀ to A₅ and therespective inverted versions of these bits and to the signal bits B₀₀ toB₂₃ through a total of twelve input lines as shown. The individualdecoder units D₀ to D₁₁ are implemented by full CMOS configuration andare operative to produce output address bits O₁ to O₁₁ in response tothe supplied address bits A₀ to A₅ and A₀ to AHD 5 basically also inaccordance with the schedules represented by the address maps depictedin FIGS. 2A and 2B.

FIG. 5 shows an example of the transistor circuit arrangementimplementing the logical configuration of the decoder circuit thusconstructed.

As shown, the three-input NAND gate G₀ of the decoder unit D₀ comprisesthree n-channel field-effect transistors N₄₀, N₄₁ and N₄₂ connected inseries between the logic inverter I₀ and ground and three p-channelfield-effect transistors P₄₀, P₄₁ and P₄₂ connected in parallel betweenthe logic inverter I₀ and a source of a supply voltage V_(CC). Thefield-effect transistors N₄₀ and P₄₀ have their gates responsive to thepredecoded signal bit B₀₀, the field-effect transistors N₄₁ and P₄₁ havetheir gates responsive to the predecoded signal bit B₁₀, and thefield-effect transistors N₄₂ and P₄₃ have their gates responsive to thepredecoded signal bit B₂₀.

The three-input NAND gate G₁ of the decoder unit D₁ comprises threen-channel field-effect transistors N₄₃, N₄₄ and N₄₅ connected in seriesbetween the logic inverter I₁ and ground and three p-channelfield-effect transistors P₄₃, P₄₄ and P₄₅ connected in parallel betweenthe logic inverter I₁ and the source of the supply voltage V_(CC). Thefield-effect transistors N₄₃ and P₄₃ have their gates responsive to thepredecoded signal bit B₀₁, the field-effect transistors N₄₄ and P₄₄ havetheir gates responsive to the predecoded signal bit B₁₀, and thefield-effect transistors N₄₅ and P₄₅ have their gates responsive to thepredecoded signal bit B₂₀.

The three-input NAND gate G₂ of the decoder unit D₂ comprises threen-channel field-effect transistors N₄₆, N₄₇ and N₄₈ connected in seriesbetween the logic inverter I₂ and ground and three p-channelfield-effect transistors P₄₆, P₄₇ and P₄₈ connected in parallel betweenthe logic inverter I₂ and the source of the supply voltage V_(CC). Thefield-effect transistors N₄₆ and P₄₆ have their gates responsive to thepredecoded signal bit B₁₀, the field-effect transistors N₄₇ and P₄₇ havetheir gates responsive to the predecoded signal bit B₂₀, and thefield-effect transistors N₄₈ and P₄₈ have their gates responsive to theoriginal input address bit A₁.

The two-input NAND gate G₃ of the decoder unit D₃ comprises twon-channel field-effect transistors N₄₉ and N₅₀ connected in seriesbetween the logic inverter I₃ and ground and two p-channel field-effecttransistors P₄₉ and P₅₀ connected in parallel between the logic inverterI₃ and the source of the supply voltage V_(CC). The field-effecttransistors N₄₉ and P₄₉ have their gates responsive to the predecodedsignal bit B₁₁ and the field-effect transistors N₅₀ and P₅₀ have theirgates responsive to the predecoded signal bit B₂₀.

As will be seen from FIG. 4, each of the two-input NAND gates G₄, G₅ andG₆ of the decoder units D₄, D₅ and D₆, respectively, comprises twon-channel field-effect transistors connected in series between each ofthe logic inverters I₄, I₅ and I₆ and ground and two p-channelfield-effect transistors connected in parallel between each of the logicinverters I₄, I₅ and I₆ and the source of the supply voltage V_(CC). Onepair of n-channel and p-channel field-effect transistors of the NANDgate G₄ have their gates responsive to the predecoded signal bit B₂₀ andthe other pair of n-channel and p-channel field-effect transistors ofthe NAND gate G₄ have their gates responsive to the original inputaddress bit A₃. One pair of n-channel and p-channel field-effecttransistors of the NAND gate G₅ have their gates responsive to thepredecoded signal bit B₂₁ and the other pair of n-channel and p-channelfield-effect transistors of the NAND gate G₅ have their gates alsoresponsive to the original input address bit A₃. Furthermore, one pairof n-channel and p-channel field-effect transistors of the NAND gate G₆have their gates responsive to the predecoded signal bit B₁₀ and theother pair of n-channel and p-channel field-effect transistors of theNAND gate G₅ have their gates responsive to the predecoded signal bitB₂₂.

As will be further seen from FIG. 4, each of the three-input NAND gatesG₇, G₈ and G₉ of the decoder units D₇, D₈ and D₉, respectively,comprises three n-channel field-effect transistors connected in seriesbetween each of the logic inverters I₇, I₈ and I₉ and ground and twop-channel field-effect transistors connected in parallel between each ofthe logic inverters I₇, I₈ and I₉ and the source of the supply voltageV_(CC). One pair of n-channel and p-channel field-effect transistors ofthe NAND gate G₇ have their gates responsive to the predecoded signalbit B₁₁, another pair of n-channel and p-channel field-effecttransistors of the NAND gate G₇ have their gates responsive to thepredecoded signal bit B₂₂, and the remaining pair of n-channel andp-channel field-effect transistors of the NAND gate G₇ have their gatesresponsive to the inverted address bit A₁. One pair of n-channel andp-channel field-effect transistors of the NAND gate G₈ have their gatesresponsive to the predecoded signal bit B₀₂, another pair of n-channeland p-channel field-effect transistors of the NAND gate G₈ have theirgates responsive to the predecoded signal bit B₁₁, and the remainingpair of n-channel and p-channel field-effect transistors of the NANDgate G₈ have their gates responsive to the predecoded signal bit B₂₂.Furthermore, one pair of n-channel and p-channel field-effecttransistors of the NAND gate G₉ have their gates responsive to thepredecoded signal bit B₀₃, another pair of n-channel and p-channelfield-effect transistors of the NAND gate G₉ have their gates responsiveto the predecoded signal bit B₁₁, and the remaining pair of n-channeland p-channel field-effect transistors of the NAND gate G₈ have theirgates responsive to the predecoded signal bit B₂₂.

As shown in FIG. 5, the two-input NAND gate G₁₀ of the decoder unit D₁₀comprises two n-channel field-effect transistors N₅₁ and N₅₂ connectedin series between the logic inverter I₁₀ and ground and two p-channelfield-effect transistors P₅₁ and P₅₂ connected in parallel between thelogic inverter I₁₀ and the source of the supply voltage V_(CC). Thefield-effect transistors N₅₁ and P₅₁ have their gates responsive to thepredecoded signal bit B₂₃ and the field-effect transistors N₅₂ and P₅₂have their gates responsive to the inverted address bit A₂. Lastly, thetwo-input NAND gate G₁₁ of the decoder unit D₁₁ comprises two n-channelfield-effect transistors N₅₃ and N₅₄ connected in series between thelogic inverter I₁₁ and ground and two p-channel field-effect transistorsP₅₃ and P₅₄ connected in parallel between the logic inverter I₁₁ and thesource of the supply voltage V_(CC). The field-effect transistors N₅₃and P₅₃ have their gates also responsive to the predecoded signal bitB₂₃ and the field-effect transistors N₅₄ and P₅₄ have their gatesresponsive to the original input address bit A₂ as shown.

It may be herein noted that FIG. 5 herein presented shows not only thegeneral circuit arrangement or interconnections between the individualtransistors used but also a preferred example of the layout of thetransistors arranged in rows and columns on a semiconductor integratedcircuit chip in conjunction with the terminals providing the supplyvoltage source and ground lines.

The active devices of the decoder circuit being thus arranged, therespective NAND gates G₀ to G₁₁ of the decoder units D₀ to D₁₁ areoperative to produce output bits O₀ to O₁₁ in accordance with theschemes represented by the following Boolean expressions:

O₀ =(A₀ ·A₁)·(A₂ ·A₃)·(A₄ ₅)=A₀ ·A₁ ·A₂ ·A₃ ·A₄ ·A₅ O₁ =(A₀ ·A₁)·(A₂·A₃)·(A₄ ·A₅)=A₀ ·A₁ ·A₂ ·A₃ ·A₄ ·A₅

O₂ =A₁ ·(A₂ ·A₃)·(A₄ ·A₅)=A₁ ·A₂ ·A₃ ·A₄ ·A₅

O₃ =(A₂ ·A₃)·(A₄ ·A₅)=A₂ ·A₃ ·A₄ ·A₅

O₄ =A₃ ·(A₄ ·A₅)=A₃ ·A₄ ·A₅

O₅ =A₃ ·(A₄ ·A₅)=A₃ ·A₄ ·A₅

O₆ =(A₂ ·A₃)·(A₄ ·A₅)=A₂ ·A₃ ·A₄ ·A₅

O₇ =A₁ ·(A₂ ·A₃)·(A₄ ·A₅)=A₁ ·A₂ ·A₃ ·A₄ ·A₅

O₈ =(A₀ ·A₁)·(A₂ ·A₃)·(A₄ ·A₅)=A₀ ·A₁ ·A₂ ·A₃ ·A₄ ·A₅

O₉ =(A₀ ·A₁)·(A₂ ·A₃)·(A₄ ·A₅)=A₀ ·A₁ ·A₂ ·A₃ ·A₄ ·A₅

O₁₀ =A₂ ·(A₄ ·A₅)=A₂ ·A₄ ·A₅

O₁₁ =A₂ ·(A₄ ·A₅)=A₂ ·A₄ ·A₅

As will be seen from the address maps of FIGS. 2A and 2B, the addressbits O₀ to O₁₁ produced by the individual decoder units D₀ to D₁₁, viz.,appearing at the output terminals of the logic inverters I₀ to I₁₁,respectively, assume logic "0" values as follows:

The output address bit O₀ assumes a logic "0" value when all of theoriginal input address bits A₀ to A₅ are of logic "0". The outputaddress bit O₁ assumes a logic "0" value when the original input addressbit A₀ is of a logic "1" value and each of the remaining original inputaddress bits A₁ to A₅ is of a logic "0" value. The output address bit O₂assumes a logic "0" value without respect to the original input addressbit A₀ when the original input address bit A₁ is of a logic "1" valueand each of the remaining original input address bits A₂ to A₅ is of alogic "0" value. The output address bit O₃ assumes a logic "0" valuewithout respect to the original input address bits A₀ and A₁ when theoriginal input address bit A₂ is of a logic "1" value and each of theremaining original input address bits A₃ to A₅ is of a logic "0" valuewithout respect to the bit O₄ assumes a logic "0" value without respectto the original input address bits A₀ to A₂ when the original inputaddress bit A₃ is of a logic "1" value and each of the remainingoriginal input address bits A₄ and A₅ is of a logic "0" value. Theoutput address bit O₅ assumes a logic "0" value without respect to theoriginal input address bits A₀ to A₂ when each of the original inputaddress bits A₃ and A₄ is of a logic "1" value and the remainingoriginal input address bit A₅ is of a logic "0" value. The outputaddress bit O₆ assumes a logic "0" value without respect to the originalinput address bits A₀ and A₁ when each of the original input addressbits A₂ to A₄ is of a logic "0" value and the remaining original inputaddress bit A₅ is of a logic "1" value. The output address bit O₇assumes a logic "0" value without respect to the original input addressbit A₀ when the original input address bits A₁, A₃ and A₄ is of a logic"0" value and each of the remaining original input address bits A₂ andA₅ is of a logic "1" value. The output address bit O₈ assumes a logic"0" value when each of the original input address bits A₀, A₃ and A₄ isof a logic "0" value and each of the remaining original input addressbits A₁, A₂ and A₅ is of a logic "1" value. The output address bit O₉assumes a logic "0" value when each of the original input address bitsA₀, A₁, A₂ and A₅ is of a logic "1" value and each of the remainingoriginal input address bits A₃ and A₅ is of a logic "0" value. Theoutput address bit O₁₀ assumes a logic "0" value without respect to theoriginal input address bits A₀, A₁ and A₃ when the original inputaddress bit A₂ is of a logic "0" value and each of the remainingoriginal input address bits A₄ and A₅ is of a logic "1" value. Theoutput address bit O₁₁ assumes a logic "0" value without respect to theoriginal input address bits A₀, A₁ and A₃ when all the remaining inputaddress bits A₂, A₄ and A₅ are of logic "1" values.

Thus, each of the decoder units D₀, D₁, D₈ and D₉ is responsive to allof the six supplied original input address bits A₀ to A₅. Accordingly,each of these decoder units D₀, D₁, D₈ and D₉ is responsive to a singleunique sequence or combination of the input address bits and isaccordingly comprised of a three-input NAND gate responsive to three ofthe predecoded signal bits alone. Each of the decoder units D₂ and D₇ isnot responsive to one of the supplied original input address bits A₀ toA₅ and is thus responsive to two different sequences or combinations ofthe input address bits. Each of these two decoder units D₂ and D₇ maytherefore be comprised of a three-input NAND gate responsive to two ofthe predecoded signal bits and one of the original input address bits.Each of the decoder units D₃ and D₆ is not responsive to two of thesupplied original input address bits A₀ to A₅ and is thus responsive tofour different sequences or combinations of the input address bits andmay therefore be comprised of a two-input NAND gate for being responsiveto two of the predecoded signal bits alone. Each of the decoder unitsD₄, D₅, D₁₀ and D₁₁ is not responsive to three of the supplied originalinput address bits A₀ to A₅ and is responsive to eight differentsequences or combinations of the input address bits. Each of thesedecoder units D₄, D₅, D₁₀ and D₁₁ may therefore be also comprised of atwo-input NAND gate for being responsive to one of the predecoded signalbits and one of the original input address bits.

From the above discussion it will have been understood that the decoderunits D₀ to D₁₁ of the decoder circuit embodying the present inventionare broken down to four different categories which consist of a firstcategory including the decoder units D₀, D₂, D₈ and D₉ each including athree-input NAND gate responsive to predecoded signal bits alone, asecond category including the decoder units D₃ and D₆ each including atwo-input NAND gate also responsive to predecoded signal bits alone, athird category including the decoder units D₂ and D₇ each including athree-input NAND gate responsive to predecoded signal bits and anoriginal input address bit, and a fourth category including the decoderunits D₄, D₅, D₁₀ and D₁₁ each including a two-input NAND gateresponsive to a predecoded signal bit and an original input address bit.In each of the decoder units D₂ and D₇ which fall within the thirdcategory, the original input address bit used directly by the decoderunit is selected from the bits other than those which have resulted inthe two predecoded signal bits used by the decoder unit. In each of thedecoder units D₄, D₅, D₁₀ and D₁₁ which fall within the fourth category,the original input address bit used is also selected from the bits otherthan those which have resulted in the single predecoded signal bit usedby the decoder unit.

As will have been seen from the foregoing description, the decodercircuit embodying the present invention is characterized in that, interalia, the predecoded signal bits are used in combination with theoriginal input address bits in most of the decoder units such as thedecoder units D₂, D₄, D₅, D₇, D₁₀ and D₁₁. For this reason, each of thedecoder units D₀ to D₁₁ of the decoder circuit embodying the presentinvention can be implemented by a two-input or three-input NAND gate andcan accordingly be composed of only two or three CMOS transistor pairsin addition to the associated logic converter. Such a configuration ofthe decoder circuit embodying the present invention is prominentlycontrasted by a prior-art address decoder circuit which includes morethan three CMOS transistor pairs as described with reference to FIG. 1.A decoder circuit according to the present invention is thusadvantageous for its simplicity of construction and accordingly for thereduced switching time achievable of the decoder circuit over aprior-art decoder circuit of the described nature. The reduction in thenumber of series connected n-channel field-effect transistors of each ofthe decoder units significantly contributes to reduction in thetransconductance (g_(m)) of the decoder unit as a whole and will make itpossible further reduce the switching time of the decoder circuit.

While the predecode circuits used in the described embodiment of adecoder circuit have been assumed to be of the two-bit predecode type,any other types of predecode circuits such as six-bit or three-bitpredecode circuits may alternatively be used in a decoder circuitaccording to the present invention.

Furthermore, all of the input lines for the original input address bitsand the inverted versions thereof have been shown connected to thedecoder circuit but, if desired, only those for the original inputaddress bits A₁, A₂ and A₃ and the inverted version A₂ of the originalinput address bit A₂ which are used directly by the decoder circuit maybe connected to the decoder circuit. In this instance, the other inputlines may be connected only to the predecode circuit PD₁, PD₂ and PD₃without being extended far to the decoder units per se.

What is claimed is:
 1. A decoder circuit for decoding differentcombinations of supplied original input signals on input signal lines,comprising at least one predecode circuit coupled to said input signallines for producing predecoded output signals on output lines of saidpredecode circuit, and a plurality of decoder units including at leastone decoder unit coupled to at least two different combinations of saidinput signal lines, and at least one decoder unit coupled to thecombination of at least one of said output lines and at least one ofsaid input signal lines.
 2. A decoder circuit for decoding differentcombinations of supplied original input signals on input signal lines,comprising at least one predecode circuit coupled to said input signallines for producing predecoded output signals on output lines of saidpredecode circuit, and a plurality of decoder units including at leastone decoder unit coupled to at least two different combinations of saidinput signal lines, at least one decoder unit coupled to selected onesof said output signal lines alone and a decoder unit coupled to at leastone of said output signal lines and at least one of said input signallines.
 3. A decoder circuit as set forth in claim 1 or 2, in which eachof said plurality of decoder units comprises a logic NAND gate.
 4. Asemiconductor decoder circuit including a plurality of decoder units fordecoding different combinations of supplied original input signals oninput signal lines, comprising:a first set of signal lines formed on asemiconductor structure, the first set of signal lines comprising afirst group of signal lines connected to a source of a firstpredetermined voltage and a second group of signal lines connected to asource of a second predetermined voltage, a second set of signal linesformed on a semiconductor structure and extending substantially at rightangles to said first set of signal lines, the second set of signal linescomprising a third group of signal lines respectively coupled to outputsignal lines having output signals predecoded from the input signals onselected ones of said input signal lines and a fourth group of signallines respectively coupled to the input signals on selected ones of saidinput signal lines, a first set of field-effect transistors selectivelyconnected in series to the source of said first predetermined voltagealong each of the signal lines of said first predetermined voltage alongeach of the signal lines of said first group, each of the first set offield-effect transistors being of one channel conductivity type, and asecond set of field-effect transistors selectively connected in parallelto the source of said second predetermined voltage along each of thesignal lines of said second group, each of the second set offield-effect transistors being of the channel conductivity type oppositeto said one channel conductivity type, the second set of field-effecttransistors having their gates selectively connected to the signal linesof said third and fourth groups, the first set of field-effecttransistors arranged along each of the signal lines of said first groupand the second set of field-effect transistors arranged along each ofthe signal lines of said second group implementing each of said decoderunits.